This invention relates generally to packaging techniques for microelectronic components and at least in certain specific applications to packaging techniques for packaging high speed dynamic random access memories ("DRAMs").
In packaging high speed devices, it is important that the leads which connect the integrated circuit chip or die to the exterior be as short as possible in order to reduce impedance, which tends to slow down the device. One approach to achieving this goal has been to place all of the high speed pins along one side of the package and to connect them to the die using short leads.
One common packaging technique is the "lead on chip" or LOC process in which a leadframe is secured between the pins and the die. Since the leadframe is a unitary device, it may readily be secured in an automated process. In conventional designs, power and ground are brought in through a pair of leadframe leads which may have a generally U-shaped configuration. Signal leads may be located inside the U-shaped configuration of the power and ground leads and all of the different leads are connected as necessary to the integrated chip or die.
As progressively higher speed devices are developed, it is important that these devices be packaged in a way that achieves the highest possible speed. Thus, there is a continued demand for packages which facilitate high speed operation from a variety of electronic components including DRAMs.